According to researchers led by Stanford’s Mohamed M. Sabry Aly, Subhasish Mitra and HS Philip Wong, your next PC could house a “skyscraper” of computer chips. The idea is to stack application processors, memory modules, and other components one on top of the other in “a revolutionary new high-rise architecture for computing,” according to the Stanford News Service.
Such an “electronic super-device” using the team’s Nano-Engineered Computing Systems Technology, or N3XT, could power a computer which combines “higher speed with lower energy use [to] outperform conventional approaches by a factor of a thousand,” Wong told Stanford’s news journal.
The researchers said that stacking chips has long been seen as a viable path towards building a more efficient, powerful computing architecture than the current template, which lays out and connects components on a flat board, like “single-story structures in a suburb”. But building a “skyscraper” of chips has thus far proven difficult using silicon-based integrated circuits (ICs), which are tough to connect reliably in a stacked structure.
Sabry Aly, Mitra, Wong, and their colleagues believe they’ve figured out a way around such issues using “new nano-materials” to construct stacked computer chips in place of traditional silicon ICs. Dubbed Nano-Engineered Computing Systems Technology, or N3XT, involves building carbon nanotube transistors (CNTs) in a stacked arrangement. The upshot is that instead of the relatively limited number of wires connected stacked silicon chips, a N3XT device could employ “millions of electronic elevators that can move more data over shorter distances that traditional wire, using less energy,” per the researchers.
Instead of adding traditional wires to connect stacked chips in a N3XT system, communication between components is built in during the actual process of fabrication. Since CNTs can be created at much lower temperatures than silicon-based transistors, it’s possible to build components on top of each other, like a processor on a memory module, while maintaining the integrity of those tiny “electronic elevators,” the researchers noted. Silicon ICs, on the other hand, have to be fabricated separately from each other and then stacked in “3D” arrangements later, which precludes integrating those interconnects from the get-go.
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