The Silicon Review
Among the spectrum of programmable solutions that include CPUs and GPUs, FPGAs offer the highest compute capacity with the lowest power profile. However, discrete FPGAs functioning as hardware accelerators alongside processors and other compute solutions can be costly and require significant board space for the FPGA plus supporting components. Integrating an FPGA chiplet and ASIC die in the same package is an ideal solution for companies looking to bring the programmability and flexibility of an FPGA to their next-generation, high-performance system-in-package (SiP) solutions. Bringing FPGA functionality closer to other system chips in the same package enables higher bandwidth, reduced system latency, and reduced system cost.
Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA and embedded FPGA (eFPGA) solutions. The company’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, datacenter, and HPC hardware accelerator boards, and best-in-class EDA software supporting all products.
Product Offerings by Achronix
Speedchip FPGA Chiplets
Speedchip FPGA chiplets are optimized for embedding in advanced system-in-package (SiP) solutions such as 2.5D via silicon interposer or an organic substrate. With Speedchip FPGA chiplets, customers define the functionality for their FPGA chiplet by specifying the number of LUTs, memory blocks, DSP blocks and I/O interfaces needed for their application. Designers have several integration options, such as the partition of the SiP sub-system using either die-to-interposer stacking or die-to-wafer stacking, where a finished die is bonded on top of a fully processed wafer. Customers will need to work with their preferred packaging system vendor to integrate the Speedchip FPGA chiplet into their SiP.
Benefits of FPGA Chiplets:
Shipping to end customers since the middle of 2016, Speedcore embedded FPGA (eFPGA) IP has brought the power and flexibility of programmable logic to ASICs and SoCs. Customers can integrate a SpeedcoreeFPGA into an SoC for high-performance, compute-intensive and real-time processing applications such as AI, machine learning, 5G wireless, networking and automotive.
There are many benefits to embedding Speedcore technology into an SoC. Compared to a separate standalone FPGA, SpeedcoreeFPGA IP offers the following:
The Speedster7t FPGA family is optimized for high-bandwidth workloads and eliminates the performance bottlenecks associated with traditional FPGAs. Built on TSMC’s 7nm FinFET process, Speedster7t FPGAs feature a revolutionary new 2D network-on-chip (NoC), an array of new machine learning processors (MLPs) optimized for high-bandwidth and artificial intelligence/machine learning (AI/ML) workloads, high-bandwidth GDDR6 interfaces, 400G Ethernet and PCI Express Gen5 ports — all interconnected to deliver ASIC-level performance while retaining the full programmability of FPGAs.
Speedster®22i HD devices are high-performance and high-density synchronous FPGAs, offering up to 1.0 million effective LUTs, 86 megabits of embedded RAM and are built on Intel’s 22nm 3-D Tri-Gate FinFET process.
Speedster22i HD devices include embedded hard IP for communication applications including 10G/40G/100G Ethernet, 100G Interlaken, PCIe Gen3 x8 and DDR3 ×72. Additionally, Speedster22i FPGAs have up to sixty-four (64) lanes of 10.375 Gbps SerDes and up to 996 high-speed general purposes I/O.
ACE works in conjunction with industry-standard synthesis tools, allowing FPGA designers to easily map their designs into Achronix FPGAs. ACE works in conjunction with industry-standard synthesis tools, allowing FPGA designers to easily map their designs into Achronix solutions. ACE includes an Achronix-optimized version of Synplify-Pro from Synopsys. Achronix simulation libraries are supported by ModelSim from Mentor Graphics, VCS from Synopsys and Riviera-PRO from Aldec. Standard RTL (VHDL and Verilog) input together with industry-standard simulation ensures that the Achronix design flow is straightforward for existing FPGA designers.
The pre-eminent leader behind the triumph of Achronix
Robert Blake is the President and Chief Executive Officer of Achronix. He has worked in the semiconductor industry for over 25 years. Prior to Achronix Semiconductor, he was the Chief Executive Officer of Octasic Semiconductor based in Montreal, Canada. Mr. Blake worked at Altera in a variety of sales, marketing and general management roles.
“Achronix is pushing the boundaries in the high-performance FPGA market to be the global leader.”