Harn Hua NG, Plunify: Founder and Chief Executive Office “Our mission is to help customers attain the highest-performing FPGA applications”

The Silicon Review

Founded in 2009 by two passionate engineers, Plunify has emerged as a key player in the realm of FPGA design optimization, simplifying the lives of users by dismantling barriers and conserving precious time and resources. The company's primary focus lies in enhancing chip design performance, particularly in the domain of FPGA applications, where the escalating intricacies of devices and design flows present annual challenges. Plunify introduced its inaugural product, the EDAxtend platform, a cloud-based solution designed to empower engineers by offloading complex chip design builds. Leveraging the cost-effectiveness of cloud computing, this platform facilitates the economical generation and analysis of data. Building on machine learning-driven insights, Plunify subsequently developed innovative products, including the InTime software.

InTime, recognized as expert software, is crafted to optimize FPGA design performance. Compatible with major FPGA tools, it operates atop them to swiftly deliver results, fostering heightened productivity. Pioneering the integration of machine learning into the chip design landscape, InTime enables companies to significantly expedite their product time-to-market and curtail development costs. Presently, Plunify operates in Singapore, Malaysia, China, and Japan, boasting Fortune Global 500 companies among its esteemed clients. The company's commitment to leveraging increasingly affordable compute resources underscores its dedication to addressing the evolving challenges posed by FPGA complexities and design flows, thereby positioning itself as an invaluable partner in the competitive landscape of chip design.

Meticulous services provided by Plunify

InTime – FPGA timing closure & optimization: InTime has built-in intelligence to predict optimized strategies for synthesis, placement and routing. It uses machine learning to actively learn from past results, improving the predictions over time. InTime can extract more than 50% increase in design performance from the FPGA tools. High resource utilization often leads to place-&-route timing issues. Or a 3rd-party IP that cannot be edited causes issues in the middle of a tight deadline. Sometimes it is just plain old “whack-a-mole” timing paths. It is simply impractical to rip up and re-optimize the users’ RTL all the time. Use InTime-optimized settings and constraints to achieve the users’ timing without changing RTL.

Previous build results, good or bad, are valuable. From re-running previously generated settings to using incremental compilation, newer design revisions can benefit from older builds without going through the entire learning process again. Of course, the more builds InTime does, the higher the likelihood of a better result becomes. Starting in InTime 2022, InTime offers an automated, congestion-aware floor planning approach. Placement and routing engines of major FPGA tools are well-tuned and robust enough in most cases. However, these engines are often inadequate for designs with high utilization and/or congestion. Floor planning is necessary to guide these engines to provide better Place & Route results.

InTime analytics help the users understand results and problems across multiple builds, instead of narrowly looking at a single build. From measuring logic vs. routing delays across “Common Critical Paths” (CCP) to “Errors and Warnings” analytics, the tool provides additional clarity on the design characteristics. InTime works locally or on multiple computers in a network, distributing builds and aggregating results across machines automatically. It is integrated with resource management software like LSF or SGE. With Plunify Cloud, the users can even offload builds to AWS without being a cloud expert.

InTime supports major FPGA tools such as Quartus Prime, Vivado, ISE and Libero. Vendor- and architecture-specific optimizations are created for Xilinx, Intel and Microchip. These optimizations tackle different devices, design characteristics, floor planning and routing problems. Think of InTime as the users’ personal support engineer.

Plunify Cloud: Cloud computing reduces the need for upfront, possibly prohibitive fixed capital investment for a project. While it is simple to start one virtual server, orchestrating, managing and maintaining stable clusters of servers is much more complex. Plunify Cloud is built for FPGA designers to easily utilize the power of cloud computing. It handles the complex technical and security aspects of managing a cloud infrastructure while simplifying access to it. With a suite of free Plunify cloud-enabled applications, any designer can quickly develop their FPGA projects on the cloud without having to be an IT expert.

FPGA Expansion Pack: The FPGA Expansion Pack for Xilinx Vivado makes it easy for the users to use the cloud. The plugin adds cloud access functionality right into the users’ Vivado toolbar. Together with a Plunify Cloud account, this plugin enables the users to conveniently offload a build in the cloud without any IT setup. The users can optimize designs on tens, even hundreds of Amazon Web Services machines at the same time.

AI Lab: Plunify’s AI Lab enables users to leverage on the cloud for their research and development needs with the maximum convenience. Without any on-premise hardware, AI Lab allows users to launch servers on major cloud providers pre-installed with software for FPGAs, GPUs and CPUs for Machine Learning. Engineers, researchers, training providers and students can benefit from a pre-configured environment without complicated hardware setups.

Meet the leader behind the success of Plunify

Harn Hua NG, Founder and Chief Executive Office

Harn Hua has more than a decade of experience in FPGA and embedded systems design at Xilinx, Inc. in San Jose, California and later on, in mobile computing platform development at Advanced Micro Devices (AMD) in Tokyo, Japan. He holds a Master’s Degree in Electrical Engineering from Stanford University and a Bachelor’s Degree in Electrical & Computer Engineering from Carnegie Mellon University, and is proficient in English, Mandarin and Japanese.