An innovator pioneering Next-Generation HPC, AI and ML: Abacus Semiconductor Corporation

Abacus Semiconductor Corporation is a young, ambitious player in the high-performance computing and artificial intelligence hardware space. Founded in 2020 by Axel Kloth, the company was born out of a deep frustration with the inefficiencies of existing AI and HPC infrastructure. Kloth, who serves as President and CEO, set out to solve a problem that plagues modern supercomputing: the bloated, power-hungry, and cost-prohibitive architecture behind most data centers today.

The current industry standard relies heavily on general-purpose GPUs and traditional CPUs, stitched together in vast server farms running on high-bandwidth connections like 100 Gigabit Ethernet or InfiniBand. While that setup technically works, it’s expensive to buy, expensive to run, and difficult to scale efficiently. Worse, it’s not particularly user-friendly. Companies with serious AI workloads often find themselves wrestling with sky-high total cost of ownership just to get a system that can deliver the performance they need. Abacus is flipping that equation. With offices in San Jose, California and Kiel, Germany, the company is developing a suite of hardware components—processors, accelerators, and smart memory systems—that are designed from the ground up for performance, scalability, and efficiency. Their core customer is the data center operator who wants to re-home or repatriate critical IT infrastructure and needs better tools to do it.

At the core of their product roadmap is a Server-on-a-Chip: a fully integrated system that includes application processor cores, offload engines for networking and storage, legacy I/O, and a purpose-built scale-out port. That scale-out port is key. It allows direct, low-latency, high-bandwidth connections to other processors, accelerators, and memory units in the Abacus ecosystem, enabling linear performance scaling without the usual networking bottlenecks. What Abacus is building isn’t just faster hardware—it’s a rethink of how AI and HPC servers should be designed. The goal is clear: make powerful computing more accessible, more efficient, and much less painful to deploy and operate.

With a focused vision and technical depth, Abacus Semiconductor is positioning itself to redefine how modern compute infrastructure is built.

In conversation with Axel Kloth, Founder, President, and CEO of Abacus Semiconductor Corporation

Your technology addresses the limitations of traditional computing architectures like von Neumann and Harvard. How does the Kloth Architecture transform performance, efficiency, and scalability in HPC and AI?

The Kloth Architecture is predicated on the insight that all supercomputers for AI and for HPC consist of hundreds, thousands and even tens of thousands of industry-standard servers with GPGPUs as accelerators, and on the fact that performance of these machines does not scale nearly linearly with the numbers of servers deployed. As a result, we have redesigned processors and accelerators and have included smart multi-homed memories into that architecture to improve performance, efficiency, and scalability in HPC and AI. This novel architecture is patent-protected and foundational. It goes beyond what von Neumann (Princeton) and Harvard architectures can achieve, both in performance and in performance per Watt as measured in a large-scale system configuration.

With growing demand for on-premises AI data centers and edge computing, how does Abacus Semiconductor Corporation’s product suite support this industry shift away from cloud dependency?

Large-scale data centers – particularly those needed for AI and for HPC – require lots of electric energy to run and cool. While the Cloud Service Providers(sometimes also called the Hyperscalers) can build their data centers close to power plants and thus have access to cheap electricity, the companies that re-home or re-patriate their data centers to on-premises locations have to be able to get along with the power and cooling constraints of their on-premises location. As such, these operators have a much more constrained power budget and cooling possibilities. At most levels of computational AI demands, the traditional CPU and GPGPU combinations cannot fulfill the requirements, and consequently the operators are looking for alternatives.

You’ve introduced innovations such as Heterogeneous Accelerated Compute™, HRAM, and Server-on-a-Chip. How do these technologies work together to redefine data processing and system architecture?

We have developed these technologies and products because we believe that any system today must be compatible with existing I/O, mass storage and ideally also all of the programming frameworks such as openCL and openACC as well as CUDA/ZLUDA and others. The Server-on-a-Chip is used as an I/O frontend for the accelerators to enable connectivity with all current and legacy I/O standards. The smart multi-homed memory – HRAM - is a dense and fast and smart memory that allows effective and efficient sharing of data across processors, accelerators and other HRAMs, to facilitate older style methods of shared data processing such as the Message Passing Interface (MPI). The Server-on-a-Chip and HRAM as well as our accelerators as a whole enable truly Heterogeneous Accelerated Compute (HAC) because it allows the workloads to be directed to the processor or accelerator that is best-suited to the execution of the task, while the HRAM allows for data sharing while keeping things secure and fast. The seamless integration of accelerators is what makes this different from today’s solutions.

Open-source compatibility is a cornerstone of your Math Processor strategy. Why did you choose openCL and openACC over proprietary solutions like CUDA, and how does this benefit users?

For proprietary solutions such as CUDA we would have to license CUDA from NVidia, and it is unlikely that we would be able to do so. In essence, that means that we can only provide CUDA function calls that are not proprietary, and that limits the use case. We will support ZLUDA, but at this time our focus is openCL and openACC. That way, our customers have the best of both workloads.

Your processors are designed for wide-ranging applications from LLM training to cryptanalysis. How do you ensure your systems deliver sustained bandwidth, scalability, and security across such diverse use cases?

The underlying math is the same for all of the above, and as such an accelerator that can execute those basic math functions is capable of effectively and efficiently working on those kinds of workloads.

Abacus Semiconductor Corporation is committed to rethinking memory architecture with HRAM. How does intelligent, multi-homed memory redefine speed, access, and efficiency in high-performance workloads?

Today, data residing in one processor is not easily shared with another processor. The HRAM and its entire approach to what memory really should be changes that. It is smart and thus is immune against attacks like Rowhammer and similar methods. It is multi-homed, meaning it can connect to multiple processors at the same time, and allow data sharing. It is keeping memory contents coherent in hardware, meaning that the processors do not have to do it.

“Our patent-protected Heterogeneous Accelerated Compute^™ technology removes the fundamental bottlenecks affecting inter-processor communication and memory access in existing systems, enabling server manufacturers to build supercomputers for AI and beyond with unprecedented scalability.”