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What do we have to say about the newly introduced Xeon D SoCs

siliconreview What do we have to say about the newly introduced Xeon D SoCs

It seems there is an adhesion among Intel’s Xeon D SoCs, supporting platforms for storage, web hosting and networking applications with actual hardware manufacturers as well as end users. Intel this month announced that there will be an expansion of these processors with innumerable models which supports Quick Assist accelerator and increased amount of 10 GbE ports. Due to higher integration the new Xeon D SoCs for networking applications simplify creation of various devices.

Here we introduce the features of the new Xeon D SoCs:

The newest Intel Xeon D-1500-series products use Intel’s prowess in highly integrated SoCs, this time powered by up to 16 of the company’s high-performance Broadwell cores, featuring a dual-channel DDR3L/DDR4 memory controller as well as rich I/O capabilities (up to 24 PCIe 3.0 lanes, 6 SATA ports, two 10 GbE ports, USB, etc.). The Xeon D SoCs support the majority of RAS capabilities of the Xeon E5 v3 processors, including ECC, MCA, PCIe ECRC (end-to-end CRC), SMM and so on. At present, Intel offers two application-specific lineups of its Xeon D SoCs: for web hosting servers and for networking devices. The latter is going to receive several new models with improved feature-set in the coming months.

Firstly, Intel plans to integrate its QuickAssist accelerator with up to 40 Gbps of compression/encryption throughput into the new Xeon D SoCs. Today, developers of network equipment have to use Intel’s discrete QuickAssist hardware to speed up compression/encryption operations, which means larger footprint, higher power consumption and additional costs. The integration of the accelerator will enable designers to reduce dimensions of their motherboards and will reduce power consumption a bit, assuming they can feed it. Since Intel does not announce prices of the new SoCs right now, it is hard to tell how the integration affects the cost of the platforms (Intel does not mention that in its documents), but usually the elimination of one component can lead to the elimination of some other parts too, so BOMs get lower.

Secondly, Intel intends to integrate four 10 GbE controllers (at present, we do not know whether they can be grouped for 40 Gbps or split for 2.5 or 5 Gbps ports) into the new Xeon D SoCs, doubling the amount of 10 GbE ports supported by today’s Xeon D processors. Obviously, for applications that need over four 10 GbE ports, Intel’s FM10000 Ethernet PHYs will still be required, but for other devices having the integration will help to reduce extra chip count. Again, the integration here could mean a reduced footprint, lower chip count and power consumption.

The new Intel Xeon D-1500 SoCs with enhanced networking capabilities are currently sampling with Intel’s customers. The chipmaker expects its clients to start launching their products based on the new processors by mid-2017. 

 

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